Day 2 (18th July, 2017): Faculty Development Program on “Analog & Embedded Systems”

Session 1: Mr. Raman Kumar (Sr. Application Engineer, Cadence Noida)

Mr. Raman has delivered talk on “ASIC Design Flow & Verification”. He has given basic idea about floor planning and layout designing along with the recent techniques used for optimized the performance of the digital systems. He also discussed about the nano-technology (10 nm), that industry is using in present time.

Session 2: Mr. Manan Jain (Product Validation Engineer II, Cadence Noida)

Talk delivered by Mr. Manan was “Analog Design Environment”, where he discussed about the Design specifications for both analog and digital systems. An overview of Virtuoso Design Environment was also briefed out which is used for custom layout designing.